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video-cd 2nd generation S1L9224x01 1 introduction the S1L9224 is a servo signal processor designed specifically for the samsung video- cd designed using the bicmos process. rf block and picture quality enhancing items are built-in. the processor is a hard-wired free-adjustment servo with the pre-signal parts adjustment point automatically adjusted. features ? focus error amplifier & servo control ? tracking error amplifier & servo control ? sled amplifier ? embedded clv control lpf ? mirror, fok, and defect detector circuit ? apc (auto laser power control) circuit for constant laser power ? double speed play available ? circuit for interruption countermeasure ? fe bias & focus servo offset free adjustment ? ef balance & tracking loop gain free adjustment ? tracking servo offset free adjustment ? enhanced auto-sequence algorithm (fast-search) ? tracking muting by window mirror ? current, voltage pick-up interaction available ? embedded rf 3t boost circuit ? enhanced rf equalize agc circuit ? built-in focus, tracking 2x filter adjust ? single power supply: +5 v ? related products - ks9287 data processor - ks9284 data processor - ka9258d/ka9259d motor driver 80-qfp-1420c
S1L9224x01 video-cd 2nd generation 2 pin configuration S1L9224 eqi rfo2 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 rfi arf arf2 eqc gnd mcp dcb frsh dcc2 dcc1 fset vdda enbr enc envo iset vreg wdck smdp smon smef defect fok mirror reset mlt mdata mck vssa asy efm2 efm istat trcnt lock fgd fs3 flb dvee febias tgu tg2 fdfct fe1 fe2 tdfct dvdd lpft te1 te2 tzc atsc teo te- feo fe- spdlo spdl- sl- slo sl+ sstop pda pdc pdb pdd f e pd ld vr vcc visel boostc2 rfl rf- rfo irf
video-cd 2nd generation S1L9224x01 3 block diagram eqi rfo2 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 rfi arf arf2 eqc gnd mcp dcb frsh dcc2 dcc1 fset vdda enbr enc envo iset vreg wdck smdp smon smef defect fok mirror reset mlt mdata mck vssa asy efm2 efm istat trcnt lock fgd fs3 flb dvee febias tgu tg2 fdfct fe1 fe2 tdfct dvdd lpft te1 te2 tzc atsc teo te- feo fe- spdlo spdl- sl- slo sl+ sstop pda pdc pdb pdd f e pd ld vr vcc visel boostc2 rfl rf- rfo irf rf i/v amp. 3t boost circuit vref gen. apc cont rf eq & agc fok detect mirror detection circuit defect detection circuit bias gen. spindle servo focus error amp febias adjust logic tracking error i/v amp e/f balance & gain adjust seld amp. efm slice & envelope efm tracking phase & gain compensation jump pulse generation offset control focus phase & gain compensation offset cancel circuit auto-sequence move system logic adjustment-free control system logic micom to servo control decoder micom data interface logic pad4 0 pad39
S1L9224x01 video-cd 2nd generation 4 pin description table 1. pin description no. pin name i/o description 1 eqi i rf agc & eqaualize input pin 2 rfo2 i rfo buffer output and rfob output for capacity merge with rfo (by micom) 3 rfi i efm comparator input pin 4 arf o rf agc & eq output pin. 5 arf2 o rf agc & eq output pin (output enable controlled by c1flag) 6 eqc i agc_equalize level control pin, vca input pin & noise eliminating cap pin 7 gnd g ground (rf block) 8 mcp i half-wave rectifier cap pin for mirror output 9 dcb i defect max duty limiting cap pin 10 frsh i focus search generating & charge/discharge cap pin 11 dcc2 i defect min duty generating dc eliminating cap pin. (connected dcc1) 12 dcc1 o defect min duty generating dc eliminating cap pin (connected dcc2) 13 fset i focus, tracking, spindle peaking frequency compensation bias pin 14 vdda p 5v power pin for servo 15 enbr i bias pin for envelope efm-slice 16 enc i rf envelope dc bias extract voltage input pin 17 envo o rf envelope output pin 18 iset i focus search, tracking jump, sled kick voltage generating bias pin 19 vreg o 3.4v regulator output pin 20 wdck i 88.2khz input pin from dsp 21 smdp i smdp input pin of dsp 22 smon i smon input pin of dsp 23 smef i external lpf time constant connection pin of clv servo error signal 24 defect o defect output pin. 25 flb i cap pin for focus loop rising low band 26 fs3 i focus loop?s high frequency gain adjustment pin 27 fgd i focus loop?s high frequency gain adjustment pin 28 lock i sled run away preventing pin (l: sled off and tracking gain up) 29 trcnt o track count output pin 30 istat o internal status output pin 31 efm o rfo slice efm output pin (to dsp) 32 efm2 o efm comparator integrating output pin
video-cd 2nd generation S1L9224x01 5 33 asy i auto asymmetry control input pin 34 vssa g servo part analog vssa power supply pin 35 mck i micom clock pin 36 mdata i data input pin 37 mlt i data latch input pin 38 reset i reset input pin 39 mirror o mirror detect output pin 40 fok o focus ok output pin 41 sstop i pick up's maximum lead-in diameter position check pin 42 sl+ i sled servo non-inverting input 43 slo o sled servo output 44 sl- i sled servo inverting input 45 spdl- i spindle amp inverting input pin 46 spdlo o spindle amp output pin 47 fe- i focus servo amp inverting input pin 48 feo o focus servo amp output pin 49 te- i tracking servo amp inverting input pin 50 teo o tracking servo amp output pin 51 atsc i anti-shock input pin 52 tzc i tracking zero crossing input pin 53 te2 i tracking servo input pin 54 te1 o tracking error amp output pin 55 lpft i tracking error integrating input pin (auto adjust) 56 dvdd p logic dvdd power supply pin 57 tdfct i defect tracking error integrating cap connection pin 58 fe2 i focus servo input pin 59 fe1 o focus error amp output pin 60 fdfct i when defect, focus error integrating cap connection pin 61 tgu i high frequency tracking gain switching cap connection pin 62 tg2 i time constant controlling tracking loop's high frequency gain control pin 63 febias i focus error bias control connect pin 64 dvee g logic dvee power supply pin 65 pda i poto-diode a & rf i/v amp1 inverting input pin table 1. pin description (continued) no. pin name i/o description
S1L9224x01 video-cd 2nd generation 6 66 pdc i poto-diode c & rf i/v amp1 inverting input pin 67 pdb i poto-diode b & rf i/v amp2 inverting input pin 68 pdd i poto-diode d & rf i/v amp2 inverting input pin 69 f i poto-diode f & tracking (f) i/v amp inverting input pin 70 e i poto-diode f & tracking (e) i/v amp inverting input pin 71 pd i apc amp input pin 72 ld o apc amp output pin 73 vr o (vcc+gnd)/2 voltage reference output pin 74 vcc p rf part vcc power supply pin 75 visel i current, voltage pick-up select command inverting control pin (pull ? down) ex) voltage type pick-up + command pull up ? current type pick-up composition current type pick-up + command pull up ? voltage type pick-up composition 76 boostc2 i rf summing amp 3t boost's cap connection pin (connected gnd) 77 rfl i rf summing amp noise eliminating cap connection pin (connected rfo) 78 rf- i rf summing amp inverting input pin 79 rfo o rf summing amp output pin 80 irf i rfo dc eliminating input pin (used in mirror, fok pin) table 1. pin description (continued) no. pin name i/o description
video-cd 2nd generation S1L9224x01 7 m icom command ($0x, $1x) tracking gain setting for anti-shock item address data istat output symbol d3 d2 d1 d0 focus control 0 0 0 0 fs4 focus on fs3 gain down fs2 search on fs1 search up fzc tracking control 0 0 0 1 anti-shock brake on tg2 gain set tg1 gain set atsc d7 d6 d5 d4 d3 d2 d1 d0 istat output anti-shock lens. brake tg2 (d3 = 1) tg1 0 0 0 1 0 1 0 1 0 1 0 1 atsc anti- shock off anti- shock on lens brake off lens brake on high freq. gain down high freq. normal gain nor- mal gain gain up item hex as = 0 as = 1 tg2 tg1 tg2 tg1 tracking gain control tg1, tg2 = 1 gain up $10 0 0 0 0 $11 0 1 0 1 $12 1 0 1 0 $13 1 1 1 1 $14 0 0 0 0 $15 0 1 0 1 $16 1 0 1 0 $17 1 1 1 1 $13, $17, $1b, $1f (as0) $13, $17, $18, $1c (as1) tracking gain up at this time, mirror muting is off $18 0 0 1 1 $19 0 1 1 0 $1a 1 0 0 1 $1b 1 1 0 0 $1c 0 0 1 1 $1d 0 1 1 0 $1e 1 0 0 1 $1f 1 1 0 0
S1L9224x01 video-cd 2nd generation 8 $2x d7 d6 d5 d4 d3 d2 d1 d0 istat output tracking servo mode sled servo mode 0 0 1 0 mode tm7 tm6 tm5 tm4 tm3 tm2 tm1 tzc tm1 $20 1 0 1 0 1 1 0 0 track. servo off $21 1 0 1 0 1 0 0 1 track. servo on $22 1 0 0 0 1 1 0 tm2 $23 1 1 1 0 1 1 0 0 sled. servo on $24 1 0 1 0 1 1 1 1 sled. servo off $25 1 0 1 0 1 0 1 tm4 tm3 track.kick $26 1 0 0 0 1 1 1 0 0 fwd. jump $27 1 1 1 0 1 1 1 0 0 jump off $28 1 0 1 0 0 1 0 0 0 rev. jump $29 1 0 1 0 0 0 0 tm4 tm3 sled. kick $2a 1 0 0 0 0 1 0 0 0 fwd. kick $2b 1 1 1 0 0 1 0 0 0 kick off $2c 1 0 1 1 1 1 0 0 0 rev. kick $2d 1 0 1 1 1 0 0 tm7 (jump) $2e 1 0 0 1 1 1 0 1 lens brake on $2f 1 0 0 1 1 1 0
video-cd 2nd generation S1L9224x01 9 tracking condition for dirc (direct 1 track jump) item hex dirc = 1 dirc = 0 dirc = 1 tm 654321 tm 654321 tm 654321 tracking mode $20 000000 001000 000011 $21 000010 001010 000011 $22 010000 011000 100001 $23 100000 101000 100001 $24 000001 000100 000011 $25 000011 000110 000011 $26 010001 010100 100001 $27 100001 100100 100001 $28 000100 001000 000011 $29 000110 001010 000011 $2a 010100 011000 100001 $2b 100100 101000 100001 $2c 001000 000100 000011 $2d 001010 000100 000011 $2e 011000 000100 100001 $2f 101000 100100 100001
S1L9224x01 video-cd 2nd generation 10 register $3x select (upper 8 bits out of 16 bits) address focus search sled kick c1 flag output defect duty 3teq speak d11 d10 d9 d8 d7 d6 d5 d4 d15-d12 0011 ps4 search+2 ps3 search+1 ps2 kick+2 ps1 kick+1 dspmc2 dspmc state equalize 3t boost sw 0: off 1: on peaking prevent standard freq. 0: 88khz 1: 44khz 0 0 0.45ms 0 1 0.54ms 1 0 0.63ms 1 1 0.73ms initial 0 1 0 0 address modec onoff tocd int3 d3: envelope efm-slice or normal efm- slice select elock h ? lock h: envelope converse d1: tracking servo offset adjust select - tocd: tracking balance, gain offset adjust select register reset command (0: reset, 1: reset cancel) tracking servo offset a adjust. (0: no used, 1: used) d3 d2 d1 d0 d15-d12 0011 efm slice 0: envel 1: normal peaking prevent 0: off 1: on tracking offset adjust 0: off 1: on focus servo cpeak mute 0: off 1: on initial 1 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 istat 0 0 1 1 focus servo search level control sled servo kick level control sstop ps4 ps3 ps2 ps1 search + 2 search + 1 kick + 2 kick + 1 data mode (level) search x1 $30 - $33 kick x1 $30, $34, $38, $3c search x2 $34 - $37 kick x2 $31, $35, $39, $3d search x3 $38 - $3b kick x3 $32, $36, $3a, $3e search x4 $3c - $3f kick x4 $33, $37, $3b, $3f data s.x1, k.x1 s.x2, k.x2 s.x3, k.x3 s.x4, k.x4 $30 $35 $3a $3f
video-cd 2nd generation S1L9224x01 11 auto sequence mode speed related command ($fx) address data 0 1 0 0 d3 d2 d1 d0 auto-sequence cancel 0 0 0 0 auto-focus 0 1 1 1 1-track jump 1 0 0 0: fwd 1: rev 10-track jump 1 0 1 2n-track jump 1 1 0 m-track jump 1 1 1 fast search 0 1 0 address data 1 1 1 1 d3 d2 d1 d0 x 1 speed 0 0 0 0 x 2 speed 0 0 1 1
S1L9224x01 video-cd 2nd generation 12 ram register set notes: actually count value can be a little error in fixed value. a fixed value + 4-5 wdck b, d, e, fixed value + 3 wdck c fixed value + 5 wdck n, m, t, p fixed value + 3 trcnt warning 1. out of the 16 settings, pwm width (pw) can select only one of 1, 2, 4, or 8 (not a 4-bit mixture) 2. when using a 2n track or an m track, more than 512 tracks is not recommended (potential for error within the algorithm) 3. there can be a 1-2 error in the wpm duty (pd), so set to fixed value + 2 4. $5xxxs i/v sel command (0: pick-up configuration using voltage 1: current-type only) 5. t.rst: 0: tracking servo offset dac value reset cancel 1: tracking servo offset dac value reset 6. efmbc: 0: double asy compen sation efm slicer 1: single asy compen sation efm slicer 7: fjts: when fast search, tracking servo off mode item data address d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 blind a, e overflow. c $5xx 0.18 ms 0.09 ms 0.04 ms 0.02 ms brake. b 0.36 ms 0.18 ms 0.09 ms 0.04 ms i/v ? 0: voltage, 1: current type t.rst ? 0: reset cancel, 1: reset tracking servo offset fast f 23.2 ms 11.6 ms 5.80 ms 2.90 ms fast k 0.72 ms 0.36 ms 0.18 ms 0.09 ms i/v sel t.rst adjust efmb c fjts ini. 1 0 1 0 1 0 0 0 0 0 0 0 kick d $6xxx 11.6 ms 5.80 ms 2.90 ms 1.45 ms efmbc: double compensation of efm asy 1: single (no used), 0: (used) fjts: fast search tracking mute 0: no used, 1: used fast r 23.2 ms 11.6 ms 5.80 ms 2.90 ms pwm duty pd 8 4 2 1 pwm width pw 5.8 ms 2.9 ms 1.45 ms 0.75 ms ini. 0 1 1 1 1 0 1 0 0 0 1 0 2n tra n m tra. m $7xxx 4096 2048 1024 512 256 128 64 32 16 8 4 2 fast search t $7xxx 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 ini. 0 0 0 0 0 0 1 1 1 1 1 1 brake point p $bxxx 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 ini. 0 0 0 0 0 0 1 1 1 0 0 0
video-cd 2nd generation S1L9224x01 13 absolute maximum ratings electrical characteristics item symbol min typ max unit supply voltage v max 5 v operating temperature t opr - 20 25 70 c storage temperature t stg - 55 25 150 c permissible loss pd 150 mw table 2. electrical characteristics no item symbol block min typ max unit 1 supply current 6v icchi supply current 15 40 60 ma 2 supply current 5v iccty 12 32 50 ma 3 supply current 4v icclo 10 25 40 ma 4 rf amp offset voltage vrfo rf amp -85 0 +85 mv 5 rf amp oscillation voltage vrfosc 0 50 100 mv 6 rf amp voltage gain grf 16.2 19.2 23.0 db 7 eq12 on flag flon 0.85 1.00 1.15 db 7-1 eq12 off flag floff - - -15 db 8 rf rhd charac. rfthd - - 5 % 9 rf amp maximum output voltage vrfpp1 3.8 - - v 10 rf amp minimum output voltage vrfpp2 - - 2.0 v 11 1x rf ac charac. rfac1 0.00 1.50 2.0 - 12 2x rf ac charac. rfac2 0.00 1.25 4.0 - 13 visel control register 1 rvisel1 35 55 85 kohm 14 visel control register 2 rvisel2 35 55 85 kohm 15 rf ivsel connection charac. ac rfselac 35 55 85 kohm 16 rf ivsel connection charac. bd rfselbd 35 55 85 kohm 17 rf ivsel connection charac. ac2 rfselac2 70 110 160 kohm 18 rf ivsel connection charac. bd2 rfselbd2 70 110 160 kohm 19 focus error offset voltage vfeo1 focus error amp -525 -250 -50 mv 20 focus error auto voltage vfeo2 -70 0 +70 mv 21 istat after febias adjust vistat1 4.3 - - v 22 focus error voltage gain 1 gfeac 18 21 24 db
S1L9224x01 video-cd 2nd generation 14 23 focus error voltage gain 2 gfebd focus error amp 18 21 24 db 24 focus error voltage gain difference cfe -3 0 +3 db 25 focus error ac difference vfeacp 0 50 100 mv 26 ferr maximum output voltage h vfepph 4.4 - - v 27 ferr minimum output voltage l vfeppl - - 0.6 v 28 agc max. gain gagc rf agc & equalizer 16 19 22.5 db 29 agc eq gain geq -1 1 2 db 30 agc normal gain gagc2 3 6 9.8 db 31 agc compress ratio cagc 0 2.5 5 db 32 agc frequency fagc -1.5 0 2.5 db 33 agc level control 1 agcl1 1.03 1.15 3 - 34 agc level control 2 agcl2 1.0 1.15 1.3 - 35 agc level control 3 agcl3 1.0 1.15 1.25 - 35-1 arf2 on flag aflon ragcf1 -0.1 0 0.1 - 36 terr gain voltage gain 1 gtef1 tracking error gain & balance -2 0.5 2 db 37 terr gain voltage gain 2 gtef2 1 1.7 2.4 - 38 terr gain voltage gain 3 gtef3 1 1.3 1.6 - 39 terr gain voltage gain 4 gtef4 1 1.45 1.9 - 40 terr gain voltage gain 5 gtef5 1 1.55 2.1 - 41 terr gain voltage gain 6 gtef6 1 1.45 1.9 - 42 terr gain voltage gain 7 gtef7 1 1.45 1.9 - 43 terr balance gain gtee 10.5 13.5 16.5 db 44 terr balance mode 1 tbe1 0.98 1.05 1.1 - 44-1 terr balance mode 11 tbe11 0.98 1.05 1.1 - 45 terr balance mode 2 tbe2 1.0 1.05 1.1 - 46 terr balance mode 3 tbe3 1.0 1.05 1.1 - 47 terr balance mode 4 tbe4 1.0 1.10 1.5 - 48 terr balance mode 5 tbe5 1.0 1.20 1.4 - 49 terr balance mode 6 tbe6 1.0 1.3 1.75 - 50 terr ef voltage gain difference gtef 10.0 13.0 16.0 db 51 terr maximum output voltage h vtpph 3.5 - - v 52 terr minimum output voltage l vtppl - - 1.5 v table 2. electrical characteristics (continued) no item symbol block min typ max unit
video-cd 2nd generation S1L9224x01 15 53 apc psub voltage l apsl automatic power control (apc) - - 1.2 v 54 apc psub voltage h apsh 3.8 - - v 55 apc nsub voltage l ansl - - 1.2 v 56 apc nsub voltage h ansh 3.8 - - v 57 apc psub voltage ldoff apslof 4.0 - - v 58 apc nsub voltage ldoff anslof - - 1.0 v 59 apc current drive h acdh 2.5 - - v 60 apc current drive l acdl - - 2.5 v 61 mirror minimum operting freq. fmirb mirror - 550 900 hz 62 mirror maximum operting freq. fmirp 30 75 - khz 63 mirror am charac. fmira - 400 600 hz 64 mirror minimum input voltage vmirl - 0.1 0.2 v 65 mirror maximum input voltage vmirh 1.8 - - v 66 fok threshold voltage vfokt fok -420 -350 -300 mv 67 fok output voltage h vfohh 4.3 - - v 68 fok output voltage l vfokl - - 0.7 v 69 fok freq. charac. ffok 40 - - khz 70 defect bottom voltage fdfctb defect - 670 1000 hz 71 defect cutoff voltage fdfctc 2.0 4.7 - khz 72 defect minimum input voltage vdfctl - 0.3 0.5 v 73 defect maximum input voltage vdfcth 1.8 - - v 74 normal efm duty voltage 1 ndefmn normal efm slice -50 0 +50 mv 75 normal efm duty symmetry ndefma 0 5 10 % 76 normal efm duty voltage 3 ndefmh 0 +50 +100 mv 77 normal efm duty voltage 4 ndefml -100 -50 0 mv 78 normal efm minimum input voltage ndefmv - - 0.12 v 79 normal efm duty difference 1 ndefm1 30 50 70 mv 80 normal efm duty difference 2 ndefm2 30 50 70 mv table 2. electrical characteristics (continued) no item symbol block min typ max unit
S1L9224x01 video-cd 2nd generation 16 81 env efm duty voltage 1 edefmn1 envelope efm slice -50 0 +50 mv 82 env efm duty voltage 2 edefmn2 -50 0 +50 mv 83 env efm duty symmetry edefma 0 5 10 % 84 env efm duty voltage 3 edefmh1 0 +50 +100 mv 85 env efm duty voltage 4 edefmh2 +160 +250 +340 mv 86 env efm duty voltage 5 edefml1 -100 -50 0 mv 87 env efm duty voltage 6 edefml2 envelope -340 -250 -160 mv 88 env efm minimum input voltage edefmv - - 0.12 v 88-1 double asy method 1 dam1 double asy method -350 -250 -150 mv 88-2 double asy method 2 dam2 150 250 350 mv 88-3 double asy method 3 dam3 -650 -500 -350 mv 88-4 double asy method 4 dam4 350 500 650 mv 89 fzc threshold voltage vfzc interface logic 35 69 100 mv 90 anti-shock detect h vatsch 7 32 67 mv 91 anti-shock detect l vatscl -67 -32 -7 mv 92 tzc threshold voltage vtzc -30 0 +30 mv 93 sstop threshold voltage vsstop -150 -65 -30 mv 94 tracking gain win t1 vtgwt1 200 250 300 mv 95 tracking gain win t2 vtgwt2 100 150 200 mv 96 tracking gain win i1 vtgwi1 250 300 350 mv 97 tracking gain win i2 vtgwi2 150 200 250 mv 98 tracking bal win t1 vtgw11 -50 0 +50 mv 99 tracking bal win t2 vtgw12 -40 0 +40 mv 100 vreg voltage vreg reference voltage 3.20 3.45 3.65 v 101 reference voltage vref -100 0 +100 mv 102 reference current h irefh -100 0 +100 mv 103 reference current l irefl -100 0 +100 mv table 2. electrical characteristics (continued) no item symbol block min typ max unit
video-cd 2nd generation S1L9224x01 17 104 f.servo off offset vosf1 focus servo -100 0 +100 mv 105 f.servo dac on offset vosf2 0 +250 +500 mv 106 f.servo auto offset vaof -75 0 +75 mv 107 f.servo auto istat vistat2 4.3 - - v 108 ferr febias status vfebias -50 0 +50 mv 109 f.servo loop gain gf 19 21.5 24 db 110 f.servo output voltage h vfoh 4.4 - - v 111 f.servo output voltage l vfol - - 0.75 v 112 f.servo maximum output voltage h vfomh 3.68 - - v 113 f.servo maximum output voltage l vfoml - - 1.32 v 114 f.servo osillation voltage vfosc 0 +100 +185 mv 115 f.servo feed through gff - - -35 db 116 f.servo search voltage h vfsh +0.35 +0.50 +0.65 v 117 f.servo voltage l vfsl -0.65 -0.50 -0.35 v 118 focus full gain gfsfg 40.0 42.5 45.0 db 119 f.servo ac gain 1 gfa1 19.0 23.0 27.0 db 120 f.servo ac phase 1 pfa1 30 65 90 deg 121 f.servo ac gain 2 gfa2 14.0 18.5 23.0 db 122 f.servo ac phase 2 pfa2 30 65 90 deg 123 f.servo mutting gmutt - - -15 db 124 f.servo ac charac. 1 gfac1 0.75 0.85 0.95 - 125 f.servo ac charac. 2 gfac2 0.68 0.78 0.88 - 126 f.servo ac charac. 3 gfac3 0.60 0.70 0.80 - 127 f.servo ac charac. 4 gfac4 0.68 0.78 0.88 - 128 f.servo ac charac. 5 gfac5 0.94 1.04 1.14 - 129 f.servo ac charac. 6 gfac6 0.73 0.83 0.93 - 130 t.servo dc gain gto tracking servo 12.5 15.0 17.5 db 131 t.servo off offset vost1 -100 0 +100 mv 132 t.servo dac offset vtdac 150 320 550 mv 133 t.servo on offset vost2 -350 0 +350 mv 134 t.servo auto offset vtaof -50 0 +50 mv 135 t.servo oscillation vtosc 0 +100 +185 mv table 2. electrical characteristics (continued) no item symbol block min typ max unit
S1L9224x01 video-cd 2nd generation 18 136 t.servo atsc gain gatsc tracking servo 17.5 20.5 23.5 db 137 t.servo lock gain glock 17.5 20.5 23.5 db 138 t.servo gain up gtup 17.5 20.5 23.5 db 139 t.servo output voltage h vtsh 4.48 - - v 140 t.servo output voltage l vtsl - - 0.52 v 141 t.servo maximum output voltage h vtsmh 3.68 - - v 142 t.servo minimum output voltage l vtsml - - 1.32 v 143 t.servo jump h vtjh 0.35 0.5 0.65 v 144 t.servo jump l vtjl -0.65 -0.5 -0.35 v 145 t.servo dirc h vdirch 0.35 0.5 0.65 v 146 t.servo dirc l vdircl -0.65 -0.5 -0.35 v 147 t.servo output voltage l gtff - - -39 db 148 t.servo ac gain 1 gta1 9.0 12.5 16.0 db 149 t.servo ac phase 1 pta1 -140 -115 -90 deg 150 t.servo ac gain 2 gta2 17.5 21.5 25.5 db 151 t.servo ac phase 2 pta2 -195 -135 -100 deg 152 t.servo full gain gtfg 29.5 32 34.75 db 153 t.servo ac charac. 1 gtac1 0.59 0.69 0.90 - 154 t.servo ac charac. 2 gtac2 0.75 0.85 0.95 - 155 t.servo ac charac. 3 gtac3 0.65 0.75 0.85 - 156 t.servo ac charac. 4 gtac4 1.30 1.35 1.50 - 157 t.servo ac charac. 5 gtac5 1.15 1.25 1.35 - 158 t.servo ac charac. 6 gtac6 1.01 1.11 1.21 - 159 t.servo loop mute tsmute -250 0 +250 mv 160 t.servo loop mute ac tsmtac 0 +50 +100 mv 161 t.servo int mute m1 tsmtm1 0 +50 +100 mv 162 t.servo int mute m2 tsmtm2 0 +50 +100 mv 163 t.servo int mute m4 tsmtm4 0 +50 +100 mv 164 sl.servo dc gain gsl sled servo 20.5 22.5 24.5 db 165 t.servo feed through gslf - - -34.5 db 166 sl.servo dc lock slock 0 +50 +100 mv 166-1 sl.servo lock 2 slock2 20.5 22.5 24.5 db table 2. electrical characteristics (continued) no item symbol block min typ max unit
video-cd 2nd generation S1L9224x01 19 167 sled forward kick vskh sled servo 0.38 0.60 0.75 v 168 sled reverse kick vskl -0.75 -0.60 -0.38 v 169 sled output voltage h vslh 4.48 - - v 170 sled output voltage l vsll - - 0.52 v 171 sled maximum output voltage h vslmh 3.68 - - v 172 sled minimum output voltage l vslml - - 1.32 v 173 sp.servo 1x gain gsp spindle servo 14.0 16.5 19.0 db 174 sp.servo 2x gain gsp2 19.0 23.0 27.0 db 175 sp.servo output voltage h vsph 4.48 - - v 176 sp.servo output voltage h vspl - - 0.52 v 177 sp.servo maximum output voltage h vspmh 3.68 - - v 178 sp.servo minimum output voltage l vspml - - 1.32 v 179 sp.servo ac gain 1 gspa1 -7.0 -3.5 0 db 180 sp.servo ac phase 1 pspa1 -120 -90 -60 deg 181 sp.servo smef gain gsmef 13.0 16.5 20.0 db 182 sp.servo ac gain 2 gspa2 -3.0 9.0 12.5 db 183 sp.servo ac phase 2 pspc2 -120 -90 -60 deg table 2. electrical characteristics (continued) no item symbol block min typ max unit
S1L9224x01 video-cd 2nd generation 20 auto-sequence this feature automatically carries out the following commands: auto-focus, track jump, and move. during auto- sequence, it latches the data when mlt is l, and outputs h when istat is l and at the end. auto focus flow chart timing chart the auto-focus carries out the focus search up by receiving the auto-focus command from micom in focus search down status. ssp is focus servo on when the internal fok and fzc satisfy the all h time set blind e (register $5x) and transfer fzc to l. then the internal auto-focus is finished, and transmitted to micom through the istat output. focus search up focus servo on no yes no yes no yes auto focus end fok = h fzc = h fzc = l repeat this action during blind "e" time set by register 5, until fok and fzc are both "h" $47 latch blind time e fok, fzc -> h search up search down $02 $03 $03 $03 $08 istat focus output fok mlt focus servo on fzc internal status
video-cd 2nd generation S1L9224x01 21 1 track jump {$48 (fwd), $49 (rev)} flow-chart timing chart track jump is carried out after receiving $48 ($49), and the blind time and the brake time is set by register $5x. note : inside () means reverse. track jump sled servo off wait brake "b" no yes wait (blind a) track rev jump track, sled servo on 1 track jump end trcnt = $48: foward jump $49: reverse jump wait using the wdck standard clock for blind "a" time, set by register 5. (1 wdck = 0.011ms) repeat checks if trcnt is continuously "h" at rising edge of wdck, during blind time "b" set by register 5. $48 ( $49) blind time a wait blind time b trcnt h continuity time tracking farward jump track servo on tracking revrese jump track servo on sled servo on sled servo off sled servo on $25 $28 ($2c) $28 ($2c) $2c ($28) $25 internal status sled output track output trcnt mlt istat
S1L9224x01 video-cd 2nd generation 22 10 track jump {$4a (fwd), $4b (rev)} flow-chart timing chart {$4a(fwd), $4b(rev), inside () is reverse} 10 track jump carries out tracking forward jump until the trcnt 5 track count. it carries out tracking reverse jump until one period of trcnt is longer than the overflow c select time, then turns the tracking servo and sled servo on. this function is to check if the actuator speed is enough to turn the servo on. track fwd jump sled fwd kick trcnt = 5 no yes wait (blind a) track rev jump, sled fwd kick track, sled servo on no yes 10 track jump end c = over flow? $4a: foward jump & kick $4b: reverse jump & kick wait using the wdck standard clock for blind "a" time, set by register 5. (1 wdck = 0.011ms) $4a: tracking rev jump & sled fwd kick $4b: tracking fwd jump & sled rev kick repeat check the trcnt 1 period using the wdck standard clock to see if it is longer than the overflow c time set by register 5. $4a ( $4b) blind time a wait trcnt 5 count tracking forward jump track servo on tracking revrese jump track servo on sled servo on sled forward kick sled servo on $25 $2a ($2f) $2a ($2f) $2e ($2b) $25 internal status sled output track output trcnt mlt over flow time c trcnt 1's time check fwd rev istat
video-cd 2nd generation S1L9224x01 23 2n track jump flow-chart track fwd jump, sled fwd kick no yes wait (blind a) track rev jump, sled fwd kick wait (kick "d") no yes track servo on, sled fwd kick tracking & sled servo on 2n track jump end trcnt = n? c = over flow? $4c: foward jump & kick $4d: reverse jump & kick wait using the wdck standard clock for blind "a" time, set by register 5. (1 wdck = 0.011ms) $4c: tracking rev jump & sled fwd kick $4d: tracking fwd jump & sled rev kick repeat check of trcnt 1 period using the wdck standard clock to see if it is longer than the overflow c time set by register 5. $4c: sled fwd kick is continuously executed for kick "d" time $4d: sled rev kick is continuously executed for kick "d" time
S1L9224x01 video-cd 2nd generation 24 2n track jump {$4c(fwd), $4d(rev), inside () is reverse} timing chart similar to 10 track. kick d time is added to the sled kick and carried out. servo is turned on after lens brake execution. $4c ( $4d) blind time a trcnt n count tracking forward jump track servo on revrese jump track servo on sled servo on sled forward kick sled servo on $25+$17 $2a ($2f) $2a ($2b) $2e ($2b) $25+$18 internal status sled output track output trcnt mlt overflow time c, check trcnt 1 period fwd rev c d during d time, sled fwd kick q data read possible $26 ($27) istat
video-cd 2nd generation S1L9224x01 25 m track jump {$4e(fwd), $4f(rev)} flow-chart timing chart {$4e(fwd), $4f(rev), inside () is reverse} sled kick is carried out by counting trcnt for the set m count value set by register 7, using the clock. track servo off, sled fwd kick no yes wait (blind a) tracking & sled servo on m track move end trcnt = m? $4e: foward jump & kick $4f: reverse jump & kick wait using the wdck standard clock for blind "a" time, set by register 5. (1 wdck = 0.011ms) count m of trcnt set by register 7. $4e ( $4f) blind time a trcnt m count tracking servo off track servo on treck servo on sled servo on sled forward kick sled servo on $25 $22 ($23) $22 ($23) $22 ($23) $25 istat sled output track output trcnt mlt fwd rev internal status
S1L9224x01 video-cd 2nd generation 26 fast search flow-chart track servo on, sled fwd kick wait (blind f) no yes track fwd jump, sled fwd kick wait (blind k) track fwd jump, sled fwd pwm kick no yes track servo on, sled rev kick wait (rev. kick "r") tracking & sled servo on fast search end trcnt = t? trcnt = p? $44: foward jump & kick $45: reverse jump & kick $44: tracking fwd jump & sled fwd kick $45: tracking rev jump & sled rev kick count p of trcnt set by register 7. repeat checks trcnt, until trcnt equals t set by register 7, like the pd and pw set by register 6, pwms duty is decided with the pws pwm1 period width used as the period, and pds high. low duty used as standard 4 bits (number selected from 0 - 15) $44: sled rev kick is continuously executed for kick "r" time $45: sled fwd kick is continuously executed for kick "r" time
video-cd 2nd generation S1L9224x01 27 timing chart suggestions for using auto-sequence ? tracking gain up and brake on ($17) must be transmitted when carrying out 1, 10, 2n, track jump, and fast search. ? the entire auto-sequence modes mlt becomes l, and the sequence process is carried out at the initial wdck falling edge after data latch. ? please judge play status not by istat, but by fok and gfs. ? tracking gain up, brake, anti-shock and focus gain down are not carried out in auto-sequence, and needs a separate command. ? if the auto-sequence does not operate as istat max time over, apply $40 and clear the ssps internal status, then try again. ? the wdck mentioned above is input from dsp as 88.2khz (2x ? 196khz). also, it is possible to choice 3 mode (88, 176, 500khz) by dsp command setting. ? 2n and m track have the potential for errors within the algorithm, when jumping more than 512 tracks, so please try to limit use for track jumps within 512. ? please limit the use of the fast-search algorithm for more than 512 tracks. $44 ( $45) blind time f trcnt p count sled servo on tracking forward jump track servo on $25+$27 $26 ($27) $2a ($2f) $26 ($27) $25+$18 istat sled output track output trcnt mlt fwd rev blind k trcnt t count kick "r" sled rev kick sled servo on sled servo on sled forward kick $5xx1 tracking servo mute sled servo pwm cont internal status
S1L9224x01 video-cd 2nd generation 28 automatic adjust command tracking balance, gain adjust tracking balance, gain adjust window apc (automatic power control) address (13bit command) address data istat trcnt d8 d7 d6 d5 d4 d3 d2 d1 d0 tracking balance $80xx - $81xx 0 0 0 b5 b4 b3 b2 b1 b0 bal trcnt initial value 0 1 1 1 1 1 address (12bit command) address data istat trcnt d7 d6 d5 d4 d3 d2 d1 d0 tracking gain $81xx - $83xx 0 0 0 g4 g3 g2 g1 g0 tgh tgl initial value 1 0 0 0 0 address data istat trcnt d3 d2 d1 d0 $84xx tracking gain adjust window trcnt: istat 0-250mv: 200mv 1-150mv: 300mv tracking balance adjust window 0: -10mv-15mv 1: -20mv-20mv focus. servo offset adjust 0: off 1: on fe.bias offset adjust 0: off 1: on $841 (f.err) $842 (f.ser) trcnt initial value 0 0 0 0 address data d7 ldon d6 pnsel d5 intc2 d4 intc tracking s. window mute (88.2khz) d3 flagsel d2 flagcon d1 flaginv d0 clock $85xx apc on/off 0: apc on 1: apc off apc p/n sel 0: psub 1: nsub 0 0 11khz - 0.7khz 0: hard control 1: micom data micom data 0: flag sw-on 1: hflag sw-off 0: falgb h: sw on 1: flag h: sw off 0: lock = 1 internal lock = 1 1: lock (0,1) 1 0 cpeak (rf) 0 1 5.5khz - 0.7khz 1 1 2.7khz - 0.7khz initial value 1 0 0 0 0 1 1 1
video-cd 2nd generation S1L9224x01 29 register set 1 register set 2 address data d7 f.ser.re sel d6 foksel d5 monitor d4 fsoc d3 dsp4 d2 dsp3 d1 dsp2 d0 dsp1 $84xx focus servo offset adjust reset 0: reset 1: reset cancel trcnt output sel (monitor:1) except for gain control ($82x-$83x) 0: fok 1: trcnt trcnt monitor select 0: test output 1: fok, tgl, trcnt ferr. offset focus offset adjust step time setup 0: 46.0ms 1: 5.80ms 92.87ms 46.4ms 23.2ms 11.6ms initial v. 1 1 1 1 0 1 0 1 trcnt select is chosen by the monitor(d1), tgl is output when tracking gain adjust command ($82x-$83x) is given. others when foksel is ?0?, fok is output to the trcnt pin, when ?1? cout is output. dsp4 - dsp1: flag hold time converse by total 16 steps. default: 0101 (58ms) address data d7 dirci d6 rstf d5 agcl1 d4 agcl2 d3 elock d2 mt0 d1 mt1 d0 mt2 ? $87xx dirc 0, 1 control febias reset 0: reset 1: reset cancel agc gain adjust d5 d4 0 0 1.6v 0 1 1.45v 1 0 1.25v 1 1 1.0v 0: off 1: on envelope lock = 1 mode conversion 0 0 0 cpeak 0 0 1 fscmpo 0 1 0 balh 0 1 1 c1flag 1 0 0 dfcint 1 0 1 fecmpo 1 1 0 ball 1 1 1 lovkg initial v. 1 1 1 1 0 1 1 1
S1L9224x01 video-cd 2nd generation 30 register set 3 register set $8fxx - tracking gservo offset adjust command address data d7 ec8 d6 ec7 d5 ec6 d4 ec5 d3 ec4 d2 ec3 d1 ec2 d0 ec1 ? $8exx track. servo freq. move ec7 ec8 0 0 1 0 0 1 1 1 track. servo freq. move freq. 1.2k 1.3k 1.4k 1.5k track. servo phase shift on/off 0: off 1: on track. servo gain shift on/off 0: off 1: on focus. servo freq. move ec4 ec3 0 0 1 0 0 1 1 1 focus. servo freq. move freq. 1.2k 1.3k 1.4k 1.5k focus. servo gain shift on/off 0: off 1: on focus. servo phase shift on/off 0: off 1: on initial v. 0 0 0 0 0 0 0 0 address data d7 test d6 ec10 d5 ec9 d4 toa4 d3 toa3 d2 toa2 d1 toa1 d0 toa0 ? $8fxx fok defect mirror output on/off 0: on 1: off front asy gain 0: 1x 1: 2x envelope gain sel 0: 2x 1: 1.5x tracking servo offset adjust command 8f (001xxxxx) $8f3f ? $8f20 (-160mv ? +160mv) adjustment window used by balance window istat output monitor - tracking offset value (+30mv - +50mv) is iedal system. after offset (0mv), adjust ($8f3f ? $8f20) upper 3-5 step. consider what to set. initial v 0 0 0 1 0 0 0 0
video-cd 2nd generation S1L9224x01 31 tracking balance adjust concept the tracking balance adjust automatically adjusts using the following process: the tracking error dc offset extracted from the pre-set dc voltage window level, and the external lpf are comparison monitored by micom. process summary tracking balance adjust is accomplished in the following manner: with the focus on and spindle servo on, the tracking and sled servo loop is turned off to make the tracking loop into an open loop. the error signal which has passed through the wide-range pick-up and the tracking error amp, passes through the external lpf to extract the dc offset. the dc offset is compared with the pre-selected window comparator level to extract the tracking error amps dc offset within the window, to inform micom using the istat that the balance adjust is complete. at this time, tracking e beam-side i/v amps gain is selected by micom, and the 6-bit resistance arrays resistance value is selected by the 6-bit control signal. the values that micom applies are 000000 ? 111111. if you select the switch, te1s dc offset increases the (2.5v- d v) ? (2.5v + d v) one step at a time, to enter the pre-selected dc window level. when it enters that level, the balance adjust is completed, and the switch condition is latched at this time. in this adjust process, the te1 signals frequency distribution is from dc to 2khz, so if dc components are included, the dc offset which passed lpf are not accurate dc values. therefore, if the frequency of the te1 signal is above 1khz, micom monitors the window comparator output. the frequency check at this time monitors the trcnt pin. balance adjust completes the adjustment when the tbal output is h. vdc < rli < rhi rli < vdc < rhi rli < rhi < vdc rho h h l rlo l h h tbal (and gate) l h l tzc mirror gain adjust 6 bit array - + - + i/v amp i/v amp 69 d ck q and logic vdc 6 bit (b5-b0) from micom 70 f e f beam e beam 30 29 lpf rhi rli rlo rho tbal istat trcnt to micom
S1L9224x01 video-cd 2nd generation 32 ? rhi: high level threshold value ? rli: low level threshold value ? vdc: window comparator input voltage ? tbal: window comparator outputs and gate output value tracking balance adjust example out of $80000 ? $81f80 128 steps, the 88 steps excepting the upper and lower 20 steps, are used ($80400- $81a80). the limit adjust flow applies the gain to $830 at the focus, tracking on point, and checks the trcnts frequency. check if 7 trcnt came in during 10 ms, and if the answer is yes, check istat, and if no, repeat the trcnt number check 3 times, then go to istat check. if the 3x repeat fails as well, increase the balance switch one step. also, just in case istat does not immediately go to h when istat checking, wait 10ms. check if it is h after the 3x repeat, and if not, increase the balance switch one step. adjust the wait mentioned above 10ms, when the system is running. average the values found by repeating the balance adjust three times. if only two out of the three tries were successful in getting a balance value, average the two values. set as balance switch, this average value, +2. this is because the balance for the system and the minus value for the dc is stable in the system. precision is important in balance adjust, and about 1-2 sec is spent as adjust time, which is accounted for.
video-cd 2nd generation S1L9224x01 33 balance adjust flowchart 1 start: $804 - environment setting focus on $08 spindle on clv-s tracking off $20 sled off gain $830 balance window level seting trcnt = 7? during 10ms istat = h? after current adjust value +2 step, adjust complete b0 to b5 switch control. 1step increase from $80400 to $81a80 other method - can balance adjust while in track move. - trcnt freq. check is easy in $f3 apply 2x mode. -10mv - +15mv $84 x0xx -20mv - +20mv $84 x1xx most select is 20mv after 10ms wait, 3times repeat check to see if 10ms istat = "h". if failure again after 3 tries, switch cahnge. 3times repeat. if failure again after 3 tries, switch cahnge. no yes yes no end repeat balance adj 3times and average the thrice- repeated balance switch value to set the balance switch. if only 2 repeats out of 3 is ok, take the average of 2 repeats.
S1L9224x01 video-cd 2nd generation 34 balance adjust flowchart 2 when executing tracking balance adjust ? the balance adjust is from $80000 to $81f80, and the switch mode is changed one step at a time by 13-bit data transmission. after adjust is completed, a separate latch pulse is not necessary. ? if the trcnt freq. is not high enough, the balance can be adjusted at $f3 applied 2x mode. ? here, we have suggested tracking off status for the balance adjust, but the same amount of flow can be balance adjusted while in track move. ? the tracking balance window select level can be selected by d2 bit out of 12-bit data. 0: -10mv - +15mv, 1: -20mv - +20mv. ? when the tracking balance adjust is complete, start the tracking gain adjust. start: $800 environment setting - focus on $08 - spindle on clv-s - tracking off $20 - sled off gain $830 balance window level seting trcnt freq is high enough? istat = h? b0 to b5 switch control. 1 step increase from $80000 to $81f80 other method - can balance adjust while moving in track move. - trcnt freq. check is easy in $f3 apply 2x mode. -10mv - +15mv $84 x0xx -20mv - +20mv $84 x1xx no yes yes 1khz check no end
video-cd 2nd generation S1L9224x01 35 tracking balance equivalant register t r a c k i n g b a l a n c e f i x e d r a n d p a r a l l e l r v a l u e v a r i a b l e r e s i s t o r ( 5 b i t ) d a t a t e 1 o f f s e t f e q a . e r e q u . 7 5 k / / 5 b i t r 5 b i t e q u . 1 3 k 2 7 k 5 6 k 1 1 0 k 2 2 0 k n o t e $ 8 0 0 3 9 1 k 5 3 1 k 6 . 2 9 k 6 . 8 7 k 1 1 1 1 1 f e q u i v a l e n t r e s i s t o r $ 8 0 1 3 9 1 k 5 2 3 . 6 k 6 . 4 7 k 7 . 0 9 k 1 1 1 1 0 $ 8 0 2 3 9 1 k 5 1 5 k 6 . 6 8 k 7 . 3 3 k 1 1 1 0 1 $ 8 0 3 3 9 1 k 5 0 7 . 5 k 6 . 8 9 k 7 . 5 8 k 1 1 1 0 0 $ 8 0 4 3 9 1 k 5 0 0 . 5 k 7 . 0 9 k 7 . 8 4 k 1 1 0 1 1 $ 8 0 5 3 9 1 k 4 9 2 . 5 k 7 . 3 3 k 8 . 1 2 k 1 1 0 1 0 e e q u i v a l e n t r e s i s t o r $ 8 0 6 3 9 1 k 4 8 4 . 8 k 7 . 5 8 k 8 . 4 4 k 1 1 0 0 1 $ 8 0 7 3 9 1 k 4 7 7 . 1 k 7 . 8 5 k 8 . 7 7 k 1 1 0 0 0 $ 8 0 8 3 9 1 k 4 6 7 . 5 k 8 . 2 1 k 9 . 2 2 k 1 0 1 1 1 $ 8 0 9 3 9 1 k 4 5 9 . 7 k 8 . 5 2 k 9 . 6 2 k 1 0 1 1 0 $ 8 0 a 3 9 1 k 4 5 1 k 8 . 8 8 k 1 0 . 1 k 1 0 1 0 1 1 ) 2 2 0 k / / 1 1 0 k = 7 3 . 3 3 k $ 8 0 b 3 9 1 k 4 4 4 . 8 k 9 . 2 1 k 1 0 . 5 k 1 0 1 0 0 2 ) 5 6 k / / 2 7 k = 1 8 . 2 1 k $ 8 0 c 3 9 1 k 4 3 7 k 9 . 6 2 k 1 1 . 0 k 1 0 0 1 1 3 ) 2 7 k / / 1 3 k = 8 . 7 7 5 k $ 8 0 d 3 9 1 k 4 2 9 . 4 k 1 0 . 0 k 1 1 . 6 k 1 0 0 1 0 4 ) 1 1 0 k / / 5 6 k = 3 7 . 1 0 k $ 8 0 e 3 9 1 k 4 2 2 k 1 0 . 5 k 1 2 . 2 k 1 0 0 0 1 5 ) ( 1 ) / / ( 2 ) = 1 4 . 5 8 k $ 8 0 f 3 9 1 k 4 1 3 . 5 k 1 1 . 0 k 1 3 k 1 0 0 0 0 6 ) ( 3 ) / / ( 4 ) = 7 . 0 9 k $ 8 1 0 3 9 1 k 3 9 8 . 4 k 1 2 . 2 k 1 4 . 6 k 0 1 1 1 1 7 ) 5 6 k / / 1 3 k = 1 0 . 5 5 k $ 8 1 1 3 9 1 k 3 9 1 . 6 k 1 2 . 9 k 1 5 . 6 k 0 1 1 1 0 8 ) ( 1 ) / / ( 7 ) = 9 . 2 2 3 k $ 8 1 2 3 9 1 k 3 8 3 . 8 k 1 3 . 7 k 1 6 . 8 k 0 1 1 0 1 9 ) 5 6 k / / 2 2 0 k = 4 4 . 6 3 k $ 8 1 3 3 9 1 k 3 7 6 k 1 4 . 6 k 1 8 . 2 k 0 1 1 0 0 a ) 5 6 / / 1 1 0 / 2 2 0 = 3 1 . 7 4 k $ 8 1 4 3 9 1 k 3 6 8 . 6 k 1 5 . 6 k 1 9 . 7 k 0 1 0 1 1 b ) 1 3 / / 5 6 / / 1 1 0 = 9 . 6 2 k $ 8 1 5 3 9 1 k 3 6 0 . 8 k 1 6 . 8 k 2 1 . 6 k 0 1 0 1 0 c ) ( 1 ) / / 2 7 k = 1 9 . 7 3 k $ 8 1 6 3 9 1 k 3 5 3 k 1 8 . 2 k 2 4 k 0 1 0 0 1 d ) 2 7 k / / 1 1 0 k = 2 1 . 6 7 k $ 8 1 7 3 9 1 k 3 4 5 k 1 9 . 8 k 2 7 k 0 1 0 0 0 e ) 2 7 k / / 2 2 0 k = 2 4 . 0 4 k $ 8 1 8 3 9 1 k 3 3 6 k 2 2 . 3 k 3 1 . 7 k 0 0 1 1 1 $ 8 1 9 3 9 1 k 3 2 7 . 9 k 2 4 . 8 k 3 7 . 1 k 0 0 1 1 0 $ 8 1 a 3 9 1 k 3 2 0 k 2 7 . 9 k 4 4 . 6 k 0 0 1 0 1 $ 8 1 b 3 9 1 k 3 1 2 k 3 2 . 1 k 5 6 k 0 0 1 0 0 $ 8 1 c 3 9 1 k 3 0 5 k 3 7 k 7 3 . 3 k 0 0 0 1 1 $ 8 1 d 3 9 1 k 2 9 7 k 4 4 . 6 k 1 1 0 k 0 0 0 1 0 $ 8 1 e 3 9 1 k 2 8 9 k 5 5 . 9 k 2 2 0 k 0 0 0 0 1 $ 8 1 f 3 9 1 k 2 8 2 k 7 5 k 0 k 0 0 0 0 0 2 5 2 k 1 3 k 2 6 k 2 5 2 k 6 . 8 k 5 b i t
S1L9224x01 video-cd 2nd generation 36 gain adjustment process summary the signal te1 output by the tracking error amp outputs resistance divide (dc+ac) passes through lpf and the dc offset extract signal (dc) difference amp. only pure ac components are compared with the pre-selected window comparators gain select value to carry out the tracking gain adjustment. the resistance divide changes the 5-bit resistance combination with the micom command, to change the gain. tracking gain adjustment is carried out in the same conditions as balance adjustment, which is: focus loop on, spindle servo on, tracking servo off and sled servo off. it adjusts the tracking error amps gain and the wide-rage pick-ups amount of reflection. the external lpfs cut-off frequency is set to 10hz - 100hz. the window comparators comparison level can be chosen from +150mv - +300mv, and +250mv - +200mv by micom command. tgl outputs +150mv and +250mv comparator output to trcnt. tgh outputs +300mv and +200mv comparator output to istat. gain adjustment is complete when the output is h. vac < gli < ghi gli < vac < ghi gli < ghi < vac tgh (istat output) h h l tgl (trcnt output) l h h te2 lpft te1 - + - + i/v amp i/v amp 69 and logic vdc controlled by 6 bit switch (b5-b0) from micom 70 f e f beam e beam 30 29 lpf ghi gli tgl tgh tgo istat trcnt to micom 1 k, 103 resistance array
video-cd 2nd generation S1L9224x01 37 when adjusting the tracking gain ? in gain adjustment, the switch mode is changed one step at a time from $83f ? $820 by 12-bit data transmission. a separate latch pulse is not needed after adjust completion. ? trcnt and tgal outputs h duty check standard is above 0.1ms. ? adjustment is carried out by choosing the most appropriate out of the 4 adjustment modes, including the ones listed above. ? the tracking balance window select level can be selected by the d3 bit out of the 12-bit data. 0: +250mv (tgl) - +200mv (tgh) 1: +150mv (tgl) - +300mv (tgh) ? when tracking gain adjustment is complete, tracking & sled servo loop on and toc read is initiated. window input tgh (pin30) tgl (pin29) ghi gli vac 1 2 3
S1L9224x01 video-cd 2nd generation 38 gain adjust proceeds from status 1 ? 2 ? 3 when the micom command carries out down command from $83f ? $820, in order. adjustment is complete when in status 2. gain adjustment method 1 micom monitors trcnts tgl output, and if the outputs h duty (0.1ms) is detected, the adjustment is complete. at this time, the window comparator level is +150mv - +300mv. gain adjustment method 2 micom monitors istats tgo output, and if the outputs h duty (0.1ms) is detected, the adjustment is complete. at this time, the window comparator level is +150mv - +300mv. gain adjustment method 3 micom monitors trcnts tgl output, and if the outputs h duty (0.1ms) is detected, the window comparator level is changed from +150mv - +300mv to +250mv - +200mv. and when micom again monitors trcnts tgl output and the outputs h duty (0.1 ms) is detected, the adjustment is complete. if you latch the former micom command value and the latter micom command values median, it is possible to gain adjust +200mv. gain adjustment method 4 micom monitors trcnts tgl output, and if the outputs h duty (0.1ms) is detected, micom command goes 1 step down, and adjustment is completed. at this time, the window comparator level is +150mv - +300mv. gain adjustment method 5 gain adjustment is set to a total of 32 steps, and gain window is set to +250mv. that is, the process starts at $83f and carries on to $820. it first sets $83f, monitors the trcnt pin and checks if 5 trcnt were detected during 10ms. if yes, adjustment is complete, and if no, carry on lowering the gain switch 1 step at a time. repeat the above process three times and set the gain adjustment switch with the average value. start: $83f - environment seting focus on $08 spindle on tracking off $20 sled off balance window level seting trcnt = h? g0 to g4 switch control. 32 step decrease from $83f to $820 if gain adjusting after balance adjustment, separate environment settings are not needed. -150mv - +300mv $84 1xxx +250mv - +200mv $84 0xxx yes no end
video-cd 2nd generation S1L9224x01 39 gain adjustment flowchart 2 start: $83f - environment seting focus on $08 spindle on tracking off $20 sled off balance window level seting 5 trcnt during 10ms? g0 to g4 switch control. 32 step decrease from $83f to $820 if gain adjusting after balance adjustment, separate environment settings are not needed. -150mv - +300mv $84 1xxx +250mv - +200mv $84 0xxx yes no average the 3 repeat executions, then gain switch setting end
S1L9224x01 video-cd 2nd generation 40 tracking gain equivalant resistance t r a c k i n g g a i n d a t a t e r r t o t . g a i n t e r r g a i n 5 b i t g a i n r a t i o c o m p a r e d v a l u e c o m b i n a t i o n v a l u e 5 . 0 k 5 . 0 k 2 . 5 k 1 . 2 5 k 0 . 7 5 k n o t e $ 8 3 f 0 . 1 0 8 9 6 k / 3 2 k - > 3 . 0 t i m e s 0 . 0 3 6 1 0 . 0 k 0 . 3 7 5 k 1 1 1 1 1 t h e g a i n r a t i o i s c a l c u l a t e d i n t h e t e 1 p i n . $ 8 3 e 0 . 3 0 3 0 . 1 0 1 1 0 . 0 k 1 . 1 2 5 k 1 1 1 1 0 $ 8 3 d 0 . 4 1 9 0 . 1 3 9 1 0 . 0 k 1 . 6 2 5 k 1 1 1 0 1 $ 8 3 c 0 . 5 7 5 1 . 1 9 1 1 0 . 0 k 2 . 3 7 5 k 1 1 1 0 0 $ 8 3 b 0 . 6 9 9 0 . 2 3 3 1 0 . 0 k 2 . 8 7 5 k 1 1 0 1 1 $ 8 3 a 0 . 7 9 8 0 . 2 6 6 1 0 . 0 k 3 . 6 2 5 k 1 1 0 1 0 $ 8 3 9 0 . 8 7 6 0 . 2 9 2 1 0 . 0 k 4 . 1 2 5 k 1 1 0 0 1 $ 8 3 8 0 . 9 8 1 0 . 3 2 7 1 0 . 0 k 4 . 8 7 5 k 1 1 0 0 0 $ 8 3 7 1 . 0 4 8 0 . 3 4 9 1 0 . 0 k 5 . 3 7 5 k 1 0 1 1 1 $ 8 3 6 1 . 1 3 9 0 . 3 7 9 1 0 . 0 k 6 . 1 2 5 k 1 0 1 1 0 $ 8 3 5 1 . 1 9 5 0 . 3 9 8 1 0 . 0 k 6 . 6 2 5 k 1 0 1 0 1 $ 8 3 4 1 . 2 7 3 0 . 4 2 4 1 0 . 0 k 7 . 3 7 5 k 1 0 1 0 0 $ 8 3 3 1 . 3 2 1 0 . 4 4 0 1 0 . 0 k 7 . 8 7 5 k 1 0 0 1 1 $ 8 3 2 1 . 3 8 9 0 . 4 6 3 1 0 . 0 k 8 . 6 2 5 k 1 0 0 1 0 $ 8 3 1 1 . 4 3 1 0 . 4 7 7 1 0 . 0 k 9 . 1 2 5 k 1 0 0 0 1 $ 8 3 0 1 . 4 9 0 0 . 4 9 6 1 0 . 0 k 9 . 8 7 5 k 1 0 0 0 0 $ 8 2 f 1 . 5 2 0 . 5 0 6 5 . 2 3 k 5 . 3 7 5 k 0 1 1 1 1 $ 8 2 e 1 . 6 1 8 0 . 5 3 9 5 . 2 3 k 6 . 1 2 5 k 0 1 1 1 0 $ 8 2 d 1 . 6 7 6 0 . 5 5 8 5 . 2 3 k 6 . 6 2 5 k 0 1 1 0 1 $ 8 2 c 1 . 7 5 5 0 . 5 8 5 5 . 2 3 k 7 . 3 7 5 k 0 1 1 0 0 $ 8 2 b 1 . 8 0 0 0 . 6 0 0 5 . 2 3 k 7 . 8 7 5 k 0 1 0 1 1 $ 8 2 a 1 . 8 6 7 5 0 . 6 2 2 5 . 2 3 k 8 . 6 2 5 k 0 1 0 1 0 $ 8 2 9 1 . 9 0 7 0 . 6 3 5 5 . 2 3 k 9 . 1 2 5 k 0 1 0 0 1 $ 8 2 8 1 . 9 6 1 0 . 6 5 3 5 . 2 3 k 9 . 8 7 5 k 0 1 0 0 0 $ 8 2 7 1 . 9 9 4 0 . 6 6 4 5 . 2 3 k 1 0 . 3 7 5 k 0 0 1 1 1 $ 8 2 6 2 . 0 4 0 0 . 6 8 0 5 . 2 3 k 1 1 . 1 2 5 k 0 0 1 1 0 $ 8 2 5 2 . 0 6 9 0 . 6 8 9 5 . 2 3 k 1 1 . 6 2 5 k 0 0 1 0 1 $ 8 2 4 2 . 1 0 8 0 . 7 0 2 5 . 2 3 k 1 2 . 3 7 5 k 0 0 1 0 0 $ 8 2 3 2 . 1 3 3 0 . 7 1 1 5 . 2 3 k 1 2 . 8 7 5 k 0 0 0 1 1 $ 8 2 2 2 . 1 6 7 0 . 7 2 2 5 . 2 3 k 1 3 . 6 2 5 k 0 0 0 1 0 $ 8 2 1 2 . 1 8 8 0 . 7 2 9 5 . 2 3 k 1 4 . 1 2 5 k 0 0 0 0 1 $ 8 2 0 2 . 2 1 9 0 . 7 3 9 5 . 2 3 k 1 4 . 8 7 5 k 0 0 0 0 0
video-cd 2nd generation S1L9224x01 41 example of system control program power on disc tray check loading focus error febias automatic control start $8780+$87f0+$841 transfer replay disc change focus offset cancel automatic control start $08+$867+(200ms walt)+ $86f+$842 transfer tracking offset cancel start $8f1f -> $8f00 (istat->h) transmission laser diode on ld on, p-sub $8560 limit sw check focusing auto-focusing $47 transmission spindle servo loop on tracking & sled loop off $20 transmission tracking balance adjust tracking gain adjust toc read ok? disc 8/12cm check play back after 100ms istat l -> h? after 100ms istat l -> h? time 100ms maximum 100ms maximum 2s maximum 300ms maximum try count 3? laser off $85c0 transmission display (no disc) standby laser off $85c0 transmission display (error), tray open standby fail no yes pass no yes close open focus ok? fok h?
S1L9224x01 video-cd 2nd generation 42 febias offset adjust micom sends the febias offset adjust command $841 to start the adjustment. in the focus error amp final output block, the focus output is compared with the 1/2 vdd. if the focus error amp output goes above 1/2 vdd, the febias offset adjust is completed. the focus offset adjusts voltage change per step is about 17mv. transition is carried out 1 step at a time from 112mv to -112mv by the total 5-bit resistance dac, and after completion, about - 8mv of offset is added to 1/2 step. normally, the offset distribution after febias offset adjust is between -8mv - +8mv. the design is such that after focus offset, you have the option to vary the febias by turning on the switch that connects the exterior and interior of the febias block (pin 63). this control signal is sev_stop, and it is switched on after focus servo offset adjust. when febias block is open, the focus error offset remains unchanged, the same as febias adjust offset. the time spent per step is 5.8ms, and since there are 5 bits, a total of 32 steps and maximum 256 ms can be spent. the adjustment is carried out by hardware, and it transitions from minus offset to plus offset. for febias offset readjust, 4-bit dac is reset by $8780, and reset can be canceled only when the $87f0-applied d2 bit goes from 0 ? 1. in order to prevent system errors such as static electricity, the febias dac latch blocks reset is not carried out by the reset block (system reset), but by micom data. 32 k 32 k 160 k - + - + 4 k 63 164 k 3 k x1 x2 x4 x8 x16 - + fcmpo 59 sev_stop vb va vc fe1 febias
video-cd 2nd generation S1L9224x01 43 febias offset setting rx vdd (5 v) febias rx febias rx 4 k vdd/2 * application when adjusting offset from 0mv - +100mv optional offset voltage (voff) vdd/2 * application when adjusting offset from -100mv - 0mv vdd - vdd/2 ( rx + 4 k ) = voff example) when power is 5 v ( 5 - 2.5 ) v ( rx + 4 k ) 4 k = voff 10 k ( rx + 4 k ) = voff
S1L9224x01 video-cd 2nd generation 44 focus offset adjust micom sends the focus offset adjust command $842 to start the adjustment. in the focus error amp final output block, the focus output is compared with the 1/2 vdd. if the focus error amp output goes above 1/2 vdd, the focus offset adjust is completed. the focus offset adjusts voltage change per step is about 40mv. transition is carried out 1 step at a time from 320mv to - 320mv by the total 4-bit resistance dac, and after completion, about +20 mvdml of offset is added to 1/2 step. normally, the offset distribution after focus offset adjust exists between -20mv - +20mv. the design is such that after focus offset, you have the option to vary the focus by turning on the switch that connects the exterior and interior of the focus block (pin 63). when febias block is open, the focus error offset is the same as febias adjust offset. the time spent per step is 5.8ms, and since there are 4bits, a total of 16 steps and maximum 128ms can be spent. also, lens-collision-sounds can be generated when adjusting the pick-up with a sensitive focus actuator, so the time division that uses 46ms per step, spending a total of 736ms, is used. that is carried out by setting the $86xs lowest d0 bit to 0. the adjustment is carried out by hardware, and it goes from minus offset to plus offset. for febias offset readjust, 4-bit dac is reset by $867, and reset can be canceled only when the $86f-applied d2 bit goes from 0 ? 1. in order to prevent system errors such as static electricity, the focus dac latch blocks reset is not carried out by the reset block (system reset), but by micom data. febias adjust febias offset is automatically adjusted from 0mv, and can be adjusted from the exterior at 100mv. when adjusting the febias at 0mv - +100mv, rx connect to vdd, and if adjusting the febias at -100mv - 0mv, rx connect to gnd. after febias offset automatic adjust is complete, the febias external resistance and focus error internal resistance is connected, so adjusting pin 63 (febias) to an optional offset value is possible. 48 + - focus phase compensation - + ps 4 3 0 0 1 1 0 1 0 1 x1 x2 x3 x4 + - + - + - 10 25 26 60 58 13 3.6k 60k fzci dfcti 48k fs4b fs3 fgd fdfct fsi 20k 470k 470k 47k fs2b 82k 40k 10k 50k 5k fs1 fset flb frch feo to digital vc 27 fgd 46k fs3 580k 47 feo
video-cd 2nd generation S1L9224x01 45 rf summing amplifier application the internal switch is for selecting the 1, 2x speed-related filter. it is on when 1x, and off when 2x. please adjust the according to the set. rfo rfl 55k 55k - + 65 66 78 58k - + 76 boostc2 vc rf- pda 2k vc 55k 55k 67 68 58k - + 2k vc 77 79 250pf 50pf 2pf 2pf 5.6k pdc pdb pdd
S1L9224x01 video-cd 2nd generation 46 rf equalize & agc the modulator output is the product of the input and vcagcs tanh term. it goes through about 3x of gain blocks, then is output to the arf pad. the output goes through the hpf with the pole frequency of 50khz, then is full-wave rectified to follow-up the rf levels peak envelope. at this time, the hpfs pole frequency is set to 50khz so that the 3t - 11t frequency components can pass without diminution. after full-wave rectification, the rf levels peak value is integrated to the 115pf cap node. if this peak voltage is smaller than the pre-determined voltage, it outputs a sinking current, and if larger, it outputs a sourcing current. the maximum current peak value is 10ua, and this current is i/v converted and applied as a modulator control voltage. when sinking, the voltage of vcagc is increased up to iout x 10k and multiplied with tanh(1-x), and when sourcing, the voltage of vcagc is decreased to iout x 10k and multiplied with tanh(1+x). at this time, x is (vcagc/2vt). overall, after detecting the 3t and 11ts level by full-wave rectification, it is compared to tanh using the modulator and multiplied to the gain to realize the wave-form equalize. the above is related to the agc concept, which means that a specific rf level is always taken. modulator 3x gain amp hpf (3db: 50khz) vo(t) = r6(5.5k/r5(7.5k) vin(t)tanh {2vt/vcagc(t)} vin(t) = 0.73x (rfo) i/v converter control range i * 10k full wave rectifier (rf peak envelope) iout = 2gm (vid/2) = gm * vid = (iref) * (vid/vt) = iref * (vp-vn)/vt if vn > vp vcagc increment (tanh (1-x)) if vn < vp vcagc decrement (tanh (1+x)) tanh 0.1 = 0.1 tanh 0.5 = 0.462 tanh 0.1 = 0.7 tanh 2.0 = 0.964 vref vp vn v = i/c (115pf) arf-agc output vin (t) vcagc (t) vo (t) + -
video-cd 2nd generation S1L9224x01 47 other block tracking error amplifier the side spot photo diode current which is input into blocks e and f, goes through the e loop i-v and f loop i-v amp. it is then converted into voltage, in order to gain the difference signal in the tracking error amp. it is micom programmed so that the balance is adjusted in e block, and gain is automatically adjusted in te1. focus ok circuit the focus ok circuit compares the dc difference value between the rfi and rfo blocks to the standard dc value. if the rf level is above standard, fok outputs l ? h to make a timing window for turning the focus on during focus search status. 16r r 2r 4r 8r i/v amp i/v amp 69 70 f e win comp - + 55 53 54 win comp b_ref_cntr g_ref_cntr gain [4:0] bal [4:0] gain up/down 29 trcnt lpft te2 te1 1/2r 40k 40k - + 90k 79 80 40k 40 rfo rfi fokb 57k - + vc + 0.625v
S1L9224x01 video-cd 2nd generation 48 mirror circuit the mirror signal amplifies the rfi signal, than peak and bottom holds it. peak hold can follow-up on defect-type traverse, and bottom hold can follow-up on rf envelope to count the tracks. the mirror output is the following: l within disc tracks, h between tracks, and h when a defect above 1.4ms is detected. efm comparator the efm comparator makes the rf signal into a secondary signal. the asymmetry generated by a fault during disc production cannot be eliminated by only ac coupling, so control the standard voltage of the efm comparator to eliminate it. 38k - + irf 17k 19k peak and bottom hold 80k - + - + - + 96k 1.5k mcp 8 39 mirror 80 - + 40k x5 rf envelope detect and asymmetry/envelope dc compensation and slice ac level summing system compensation asy. dc asy 33 efm2 32 efm 31 17 16 15 3 enc envo envr rfi
video-cd 2nd generation S1L9224x01 49 defect circuit after rfo signal inversion, bottom hold is carried out using only 2. except, the bottom hold of holds the coupling level just before the coupling. differentiate this with the coupling, then level shift it. compare the signals to either direction to generate the defect detect signal. apc circuit if you operate the laser diode in constant current, since it has a negative temperature characteristic with a large, it is controlled by the monitor photo diode so that the output is kept regular. dcc1 dcc2 75k - + 75k 37.5k 28k 79 bottom envelope hold bottom envelope hold - + 43k 12 11 9 24 vc+0.6254v vc defect rfo dcb - + - + 150k 150k 300k 150k 0.75k 5.5k ldon 71 72 pn pd
S1L9224x01 video-cd 2nd generation 50 center voltage generation circuit this circuit makes the center voltage using the resistance divide. rf equalize circuit the agc block maintains a steady rf peak to peak level, and has a built-in 3t gain boost function. it detects the rf envelope and compares it with the standard voltage to perform comparison gain adjustment. the received rf output stabilizes the rf level to 1vpp, and this output is applied as the efm slice input. eq12 (input) and arf (output) on/off is to select by defect duty check of internal c1flag signal. - + 30k 30k vc 73 equalize 6 4 1 eqc arf eqi 2 eqi2 vca 5 arf2
video-cd 2nd generation S1L9224x01 51 atsc the detect circuit for the tracking gain up (about shock) is composed of a window and a comparator. - + - + bpf 51 tracking gain up atsc
S1L9224x01 video-cd 2nd generation 52 focus servo if set to phase compensate the focus servo loop, the focus servo loop is muted when defect is h. at this time, the focus error signal is integrated by the 0.1uf capacitor to be connected to the fdfct block, and the 470k ohm resistance. it is then output through the servo loop. therefore, during defect, the focus error output is held as the error value before the defect error. the frequency which maximizes the focus loops phase compensation is changed by the fset block. if the resistance is 510 kohm, the maximum frequency is 1.2khz, and is inversely proportional to the resistance. when in focus search, fs4 is on to intercept the error signal. the focus search signal is output through the feo block. when focus is on, fs2 is on, and the focus error signal input through the fe2 block is output to the output pin through the loop. 82k 20k focus phase compensation 58 25 60 fe2 fgd 10 feo to digital 13 - + 3.6k 3.6k 48k fs4b 27 dfct1 26 160k 470k 40k 40k 10k - + 50k 5k - + vc - + - + 48 580k 46k fs3 fs3 fdfct fs2b flb frch fset fe- 47 fs1 fzci
video-cd 2nd generation S1L9224x01 53 tracking servo after tracking servo loops phase compensation and during defect, the tracking error signal is integrated through 470k resistance and the 0.1uf capacitor, then output through the servo loop. rtg and tg2 blocks are tracking gain up/down exchange blocks. in phase compensation, like focus loop, the peak frequency of the phase compensation is varied by the fset block. if the resistance connected to the fset block changes, the op amp dynamic range and the offset change as well. the tm7 switch is a brake switch which turns the tracking loop on/off when the actuator is unstable after a jump. after the servo has jumped 10 tracks the servo circuit is out of the liner range, and sometimes the actuator follows an unstable track. so this prevents unnecessary jumping caused by unwanted tracking errors. tg2 and tgu blocks adjust the tracking servo loops high frequency gain. it adjusts the gain of the wanted frequency band zone through the external cap. 53 57 te2 tdfct tracking phase compensation 470k 680k dfct1 61 680k 10k 68pf 110k 82k 20k tm1 470k 62 10k 90k tm7 - + 50 13 49 tg2b tg1 tg1b tm3 tm4 fset tgu tg2 te- teo
S1L9224x01 video-cd 2nd generation 54 sled servo this servo integrates the tracking servo output to move the pick-up. also, during track movement, it outputs sled kick voltage for the track jump along the sled axis. spindle servo & low pass filter 200hz lpf is configured by the 20k resistance and 0.33uf cap in order to eliminate carrier components. fsw becomes low in clv-s mode, so more powerful filter movements are carried out. 39 sl+ + - 37 slm tm6 tm7 38 slo tm2 ps 4 3 0 0 1 1 0 1 0 1 x1 x2 x3 x4 220k - + 220k 220k 220k 15k 50k 100k 15k 22k 22k 20k - + spdlo fvco double speed 46 spdl- 45 22 21 smon smdp
video-cd 2nd generation S1L9224x01 55 item1. mirror mute (used for tracking mute only) this circuit is used as an abex-725a countermeasure, which handles tracking muting when mirror is detected. its min and max are set, and it detects a minimum of 11khz to a maximum of 700hz. except, mute does not function in the following four cases. ? when transmitting a micom tracking gain up command (tg1, tg2 = 1) ? when anti-shock is detected (atsc) ? when lock falls to l ? when defect is detected item2, trcnt output trcnt is an output generated by mirror and tzc. mirror is a track movement detect output by the main beam, and tzc is a track movement detect output by side beam. trcnt receives these 2 inputs and determines if the pick- up is currently moving inwards or outwards to use it when in tracking brake of $17. mirror mute operating/apc p-sub apc on apc off interruption on (mirror 11khz - 0.7 khz) $854 $85c interruption off $856 $85e interruption on (mirror 2.75khz - 0.7khz) $857 $85f interruption on (mirror 5.5khz - 0.7khz) $855 $85d d tzc edge detect by inverter elay tzc rising, falling detect tzc output mirror value is output at tzc rising, falling detect mirror tzc ck q

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